Technical Program Manager III, Foundry Commodity Management, Cloud Supply Chain

Technical Program Manager III, Foundry Commodity Management, Cloud Supply Chain

A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.

As the Technical Program Manager, you will be responsible for managing external Foundry relationships and collaborating with key suppliers and partners. In this role, you will be instrumental in the design, verification, and implementation of digital integrated circuits from concept to production, with a focus on ensuring seamless integration and positive outcomes with external technology providers. You will work on technologies that are critical to the next-generation products, contributing to the full lifecycle of ASIC development while managing the external technical engagements.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Minimum Qualifications:

• Bachelor's degree in a technical field, or equivalent practical experience.
• 5 years of experience in program management.
• Experience in ASIC/chip design with leadership and technical ownership.
• Experience with industry-standard EDA tools for RTL simulation, synthesis, and static timing analysis.

Preferred Qualifications:

• 5 years of experience managing cross-functional or cross-team projects.
• Experience with design for testability (DFT) concepts and methodologies (e.g., scan, JTAG, MBIST).
• Experience with embedded processors (e.g., ARM, RISC-V).
• Experience with UVM/OVM or other advanced verification methodologies.
• Experience with scripting languages (e.g., Python, Perl, Tcl) for automation of design flows.
• Knowledge of physical design concepts (e.g., floor planning, place and route, clock tree synthesis).

Responsibilities:

• Collaborate with system architects and cross-functional teams to define chip-level and block-level specifications, micro-architectures, and design partitioning.
• Participate in pre-silicon verification activities, including testbench development, simulation, and debugging, ensuring functional correctness and performance.
• Perform logic synthesis, static timing analysis (STA), and work with physical design teams to achieve timing closure, power optimization, and area goals.
• Incorporate Design-for-Test (DFT) features such as scan chains, JTAG, and MBIST to enable efficient test and debug of the silicon.
• Collaborate with post-silicon validation teams to bring up, debug, and characterize new silicon, identifying and resolving any issues.