Wireless SoC Design Engineer

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.

Description

Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions alongside software and firmware engineering teams. Collaborate with physical design, design for testability (DFT), power management, and computer-aided design (CAD) teams to finalize and deliver fully functional IP for SoC integration. Provide support to verification, prototyping, and emulation teams during pre-silicon verification phases, as well as software/firmware development. Assist in post-silicon validation, system integration, and debugging efforts, and address any necessary silicon design revisions promptly.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.

Preferred Qualifications

• Proficient in digital design fundamentals, with a strong foundation.
• Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs.
• Knowledgeable about the ASIC design flow, including System Verilog RTL implementation, Lint, Synthesis, STA, and LEC.
• Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI is a plus.
• Thorough understanding of cross clock-domain design principles and associated CDC requirements.
• Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis, is a plus.
• Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques.
• Strong communication skills, both written and oral.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

#J-18808-Ljbffr