Senior Design Verification Engineer, Silicon

Senior Design Verification Engineer, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
• Experience developing and maintaining verification test benches, test cases, and test environments.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in different verification techniques and methodologies including formal, Gate-Level Simulation, Unified Power Format based Power simulations, UVM and C based testing, to achieve bug-free Silicon in SoCs.
• Experience in Advanced RISC Machine (ARM) and RISC-V processor based Design Verification including tool chains and C based testing.
• Experience in low-power design verification.

Responsibilities

• Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA) and formal tools.
• Debug tests with design engineers to deliver design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Participate with architecture, design teams, and other teams in defining the overall verification strategy of our SoCs.