Senior Analog/mixed-signal IC Design Engineer - Acacia

Senior Analog/mixed-signal IC Design Engineer - Acacia

Apply (

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  Location:San Jose, California, US

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  Alternate LocationUnited States

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  Area of InterestEngineer - Hardware

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  Compensation Range USD- USD

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  Job TypeProfessional

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  Technology InterestCloud and Data Center

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  Job Id

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The application window is expected to close on 9/31/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.

Meet the Team

We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design.

Your Impact

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  You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products.

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  You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production.

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  You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.

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  You will develop high speed AMS circuits and best-in-class products that push the boundaries of what is possible.

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Minimum qualifications:

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  BSEE degree with 12+ years of experience or equivalent or an MS degree with 8+ years of experience, or equivalent or a PhD with 5+ years of experience, or equivalent

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  Design, simulation and measurement of high speed ICs in at least 3 areas below:

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High Speed Serial Links utilizing serializers, deserializers, and data converters, voltage regulators, output drivers, phase locked loops, clock transmission/propagation, Opamps, programmable gain amplifiers, and equalization

Preferred qualifications:

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  Experience with electrical transceiver applications including backplane and cable communications

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  Experience with FinFET technology

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  High-frequency layout experience a plus: Passive component design: inductors,

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  transformers, transmission-lines, etc.

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  Floorplanning (power/ground, digital/analog signal routing, etc.) experience

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  Custom transistor layout experience

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  Experience designing for manufacturability

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  Experience with ESD laboratory practices and methodology

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  Experience with Cadence (virtuoso), Spectre/APS/SpectreX, Matlab, EMX

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  Experience with mixed-signal simulations in AMS

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Why Cisco?

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees haveaccess ( to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings.

Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco's flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco's Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community.

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.75% of incentive target for each 1% of revenue attainment up to 50% of quota;

1.5% of incentive target for each 1% of attainment between 50% and 75%;

1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

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